The design rule for high-integrated memory devices is generally declining, from approximately 1 .mu.m for the generation of 1 Mbit-grade dynamic random access memory (DRAM) devices, to approximately 0.15 .mu.m for Gbit-grade DRAMs. As the design rule decreases, the size of the contact holes used to connect storage capacitor structures in DRAMs generally decreases as well, with an accompanying increase in aspect ratio aspect ratio of the contact hole. The decreasing area, coupled with the increasing aspect ratio, may impose a large burden on the capabilities of photolithography. Alignment margins are generally decreased, which may affect yields.
Development work on DRAMs has concentrated on enhancing capacitance in a limited unit area, and has led to the development of stacked or trench capacitor structures which replace traditional planar capacitors. The stacked capacitor structure has been further developed into a cylinder type or fin type capacitor in order to enhance the surface of the capacitor electrode. From a processing standpoint, cylinder type structures can be divided into two main classes, capacitors formed over a bitline (COB), and capacitors formed under a bitline (CUB). The COB structure enables a capacitor to be formed regardless of bitline process margin, and thus may enhance capacitance within the limited area. However, in the COB structure, the process margin for electrically connecting a storage node with a source region of a transistor is limited by the design rule of the bitline.
FIG. 1 is a cross-sectional view of a DRAM cell manufactured by a conventional method, including a semiconductor substrate 10, a field region 12, a source region 13, a first dielectric film 14, a bitline 16 formed of polycide including accumulated layers of polysilicon and silicide, a capping insulating layer 17, a second dielectric film 18, a spacer 21, and a storage node 23. According to some conventional methods, to obtain alignment margin of the BC process, self-alignment using the bitline 16 is used. To prevent bitline 16 from being shorted storage node 23, a spacer 21 is provided at the sidewall of the contact hole.
However, when forming a BC according to the conventional method for a design rule appropriated for a Gbit-grade DRAM, the aspect ratio of the BC may be equal to or greater than 6. Because of this, it may be difficult to expose the source region 13 without overetching adjacent structures. In addition, the diameter of the BC may be too small to form spacer the spacer 21. Thus, not only alignment margin but also etching margin is important for deep submicron devices.
FIG. 2 is a cross-sectional view of a DRAM cell manufactured by another conventional technique. According to this technique, a conductive pad 25 is used to reduce the aspect ratio of the BC and thus ameliorate some of the difficulties which may be involved in dry-etching the BC. The conductive pad 25 and a similar conductive pad for connecting the bitline are typically concurrently formed, so that etching depth is reduced when forming the BC, thus allowing etching margin to be maintained. Unfortunately, however, density of integration may be limited, as a stringer or bridge may be generated between the pads as the interval between the conductive pads is further reduced.